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Altera_Forum's avatar
Altera_Forum
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18 years ago

Is SystemVerilog Catching on for Design

Hello, I'd like to know how how popular SystemVerilog is today, how many people are switching from Verilog to SV? I'm pretty much a AHDL guy but I've been trying to teach myself Verilog. One thing th...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

hi guys,

actually SystemVerilog is not an HDL language for designing and synthesizing a circuit. it "adds" some system-level features to a lower-level language like verilog, which is good for describing a system or performing verification of the designs.

in contrast, a language like SystemC adds a lower-level features to higher-level language (C++) to accomplish the same thing.

adel