Forum Discussion
Altera_Forum
Honored Contributor
17 years agohi guys,
actually SystemVerilog is not an HDL language for designing and synthesizing a circuit. it "adds" some system-level features to a lower-level language like verilog, which is good for describing a system or performing verification of the designs. in contrast, a language like SystemC adds a lower-level features to higher-level language (C++) to accomplish the same thing. adel