Forum Discussion
6 Replies
- Altera_Forum
Honored Contributor
As posted before ...
There is an OpenCores project that is called "Zet PC platform" that runs Windows 3.0 Opencores has a link to this web page... http://zet.aluzina.org/index.php/pictures (http://zet.aluzina.org/index.php/pictures) This project has a SDRam IP you could try. you need to download the sources and look for "yadmc" that is the sdram controller ip. this project shows how to use this ip and parametrize it for your own sdram devices without sopc - Altera_Forum
Honored Contributor
sorry but i see only pitcures...
can you post the link of the project? - Altera_Forum
Honored Contributor
i've found it.
Thank you so much. It is in verilog language. My project is in vhdl language. Can i mix vhdl and verilog files in my project? - Altera_Forum
Honored Contributor
yes you can :)
Quartus is able to compile a mix of VHDL & verilog HDL as well as schematic entry and Altera HDL - Altera_Forum
Honored Contributor
But Modelsim will not be able to simulate a mixed VHDL/Verilog design if you don't pay an extra license, IIRC.
- Altera_Forum
Honored Contributor
That is correct, but it has been discussed on nios forum (if i am right) wheter this is still true or not. i can't remember that somebody said it is still so as it was all those years VHDL or Verilog HDL with this license
a couple of years ago you had to decide what kind of license (VHDL / verilog) you want for modelsim each time you ask altera for an updated license.