Honored ContributorThe longest signal is TCK, which is about 19 inch. And the shortest signal is TDI, which is about 7 inch.
There are 2 FPGAs in chain. Any suggestions would be help for me! Thanks Jerry
Honored Contributorthat's quite a bit of skew between the two
Honored ContributorDo the math!
I count for 70ps/cm on FR4 material, it would be 175ps/inch=>10 inch=1.75ns. The speed of jtag is for eg the usb blaster 6MHz <10Mhz=100ns. So i conclude: SKEW wont kill your design problably. On the other hand i know test systems that go up to 100MHz=10ns and then you could (i say could!) have a problem.... Anyway most of the problems i know with stability and SI of jtag are related to the multiple end points together with cables. Since you get reflections that could/will lead to stability issues. FPGA's will take clock reflections as transitions. Add some extra noise by using connectors, and cables in noisy production/ lab enviroment and spice it with a JTAG protocol that is not error tolerant and you get... TROUBLES. So my advice use a clock buffer at the connector of your jtag port to avoid a lot of problems. After you've done this there is plenty of time to worry about skew:-). Proposed Topology for the clock: Connector --short line-> BUFFER with 2 outputs | --long line--> FPGA1 | -- long line-->FPGA2 On other lines buffers are not needed except if you would connect many devices. Note that buffers will introduce even more skew.... but i would not worry about it.
