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Altera_Forum's avatar
Altera_Forum
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16 years ago

Is it safe to use 1.22V for C3 Vccint?

I'm putting together an Ethernet board that is almost done - but there isn't enough room for a full set of switching power supplies. (I'm trying to keep the board under 13sq.in)

I've settled on a master 5V switching supply, and linear regulators to generate 3.3, 2.5, and 1.2V; and I placed ST LD393000 series DPAK's on the board. They can source 3A of current, and appear to be efficient enough to keep from crisping the board.

The problem is that the smallest one is actually a 1.22V, not a 1.2V regulator. The datasheet guarantees regulation within 1.5% at 25degC, which is still under the absolute max of 1.25V.

The next suitable DPAK regulator is a Maxim part, and sources 1.5A. The Maxim regulator, however; will generate more heat and has slightly worse regulation.

The PHY will pull 500mA from the 1.2V rail in Gigabit mode, and the Cyclone III (EP3C16E144C7) is the only other major part on the board. I can only estimate how much current the FPGA will draw, but the estimator is running about 500mA for Vccint based on what I've got in there so far.

The other option is to use the LDO output on the PHY to generate a local 1.2V plane for the PHY, which would allow me to use a lower capacity regulator for the FPGA - at the cost of additional components on the board. I'm working on a branch that does this to see how bad the damage will be.

Any thoughts?

7 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    What's the regulation accuracy of the regulator on the whole temperature range? You can expect the board to be a bit warmer than ambient, and the 1.22V could get out of the acceptable range.

  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    Regulation was specified at 1.5% max, but I punted anyway.

    Instead, I used the local LDO option on the PHY, which allows the PHY to generate it's own 1.2V core voltages; and slaved a 1.2V linear off of the 2.5V rail for the FPGA. The PLL's use, at most, 100mA out of the 3A; so there is plenty of capacity left for Vccint.

    I picked a part with a 1.2V dropout, so it shouldn't be an issue - and the self-heating should be minimized by the small Vin-Vout. All of the parts were available in DPAK packages with the exception of the FET for the PHY's LDO - which was in an SC-70-6 package. Size-wise, it added a bit of area - but in an part of the board that was not very dense to begin with.

    I only hope the FPGA doesn't pull more than 1A on Vccint. I can't seem to find a "worst case" current draw for Vccint in the data sheet. I used the spreadsheet, but I'm not sure if I really gave it a true "worst case".
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    Although a C3 FPGA device doesn't draw more than 1A on Vccint after power-up, it is probably a good idea to design the Vccint rail up to 2-3A for in-rush current. Linear regulators will end up with big heat sinks. I will use TI TPS75003RHLR to provide 3.3V, 2.5V and 1.2V from a 5V rail. I think that 1.2V +-5% should be acceptable in any case as long as it is stable and clean.

  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    --- Quote Start ---

    Although a C3 FPGA device doesn't draw more than 1A on Vccint after power-up, it is probably a good idea to design the Vccint rail up to 2-3A for in-rush current. Linear regulators will end up with big heat sinks. I will use TI TPS75003RHLR to provide 3.3V, 2.5V and 1.2V from a 5V rail. I think that 1.2V +-5% should be acceptable in any case as long as it is stable and clean.

    --- Quote End ---

    Hmm, that's a pretty good call. Soldering will be fun, but I believe our tech could probably handle a QFN. I'll have to ask him.

    Is the max inrush stated anywhere? I check the handbook, and couldn't find that figure.
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    --- Quote Start ---

    Although a C3 FPGA device doesn't draw more than 1A on Vccint after power-up, it is probably a good idea to design the Vccint rail up to 2-3A for in-rush current.

    --- Quote End ---

    There's no inrush current with C III devices. Since CII, VCCINT power-up current is guaranteed to be below the static idle current of the device. You can achieve VCCINT considerably above 1 A with designs that have very high system clocks and and a high register toogle rate. But this is unlikely to happen in typical designs.
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    Suppose that you will have plenty of capacitors on power rails to keep power clean. They mainly cause in-rush current during power-up. As to in-rush current of C3 devices themselves, Fvm has answered your question. Please refer to the hot pluggable section of C3 data sheets or operation manual.

  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    I appreciate the answer. I've already bitten the bullet, and redesigned the power supply. I'm not using the TI part, but I am going with switchers for the 3.3 and 1.2V rails. I did end up going with a small LDO for the Vccaux, about 350mA.

    It's a bit of a pain, but I'd rather have a stable, cool power supply for the board - particularly if I end up doing the add-in board.