Is it safe to use 1.22V for C3 Vccint?

Regulation was specified at 1.5% max, but I punted anyway.

Instead, I used the local LDO option on the PHY, which allows the PHY to generate it's own 1.2V core voltages; and slaved a 1.2V linear off of the 2.5V rail for the FPGA. The PLL's use, at most, 100mA out of the 3A; so there is plenty of capacity left for Vccint.

I picked a part with a 1.2V dropout, so it shouldn't be an issue - and the self-heating should be minimized by the small Vin-Vout. All of the parts were available in DPAK packages with the exception of the FET for the PHY's LDO - which was in an SC-70-6 package. Size-wise, it added a bit of area - but in an part of the board that was not very dense to begin with.

I only hope the FPGA doesn't pull more than 1A on Vccint. I can't seem to find a "worst case" current draw for Vccint in the data sheet. I used the spreadsheet, but I'm not sure if I really gave it a true "worst case".