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Altera_Forum
Honored Contributor
Honored ContributorIs it possible to write this?
Hello, I have to write a VHDL code in which i wrote case statement two times for the same FSM states(case statement was in fact interrupted by an if statement).Please look at the underlined lines ...
Altera_ForumHonored Contributor
Honored ContributorI think, the shown code isn't legal VHDL because each case statement must either cover all possible state alternatives or contain an others case. It's no problem to supplement the code respectively, but the design is at least rather confusing. Thus I would also suggest to merge the code into one case statement.
