Forum Discussion
Altera_Forum
Honored Contributor
Honored ContributorIs it possible to write this?
Hello, I have to write a VHDL code in which i wrote case statement two times for the same FSM states(case statement was in fact interrupted by an if statement).Please look at the underlined lines ...
Altera_ForumHonored Contributor
Honored ContributorFrom what I see in your schematic you can put the if statement inside the Stop_Cond_3 state.
You should also initialize all your variables somewhere. I guess setting them to 0 in the Idle state should do the trick.
