Forum Discussion
JBoot1
New Contributor
New ContributorIs it possible to use the FLR for the HIP PCIe AVST core to reset logic?
I have an endpoint design which uses the hard IP PCIe avalon-st core with multiple functions. One of the functions is used by a VM so I would like to enable the function level reset for that functi...
SengKok_L_Intel
Regular Contributor
Regular ContributorHi,
If you are using PCIe AVST SRIOV IP, then it is possible for the FLR.
Assuming you are using Arria 10 device, you can refer to the link below (section 5.7 & 7.2) for the detail:
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_a10_pcie_sriov.pdf
Regards -SK
