Is it possible to make a bottom level design

There are no gates inside a FPGA which can be re-arranjed.

There are just logic elements which can be programmed in different ways.

If you want to create delay lines, you can use use LCELL or CARRY primitive.

You can also use a family specific primitive, such as "cycloneiii_lcell_comb", but the above ones should be good enough.

--- Quote Start ---

I am a student and recently my professor ask me to see if it is possible to create delay lines with FPGA ( by cascading buffers or inverters together ) so that we may be able to test chip delays with such a tool.

--- Quote End ---

Yes it is, but the stability of the delay might not be acceptable. The delay will be a function of the fabrication process, the supply voltage and the local die temperature.

--- Quote Start ---

which means that I need to modify those gates inside a FPGA directly and somehow arrange them together to generate different delays.

--- Quote End ---

That's correct, you will likely need to hand pick locations.

--- Quote Start ---

I do have experience of programming FPGA with altera tools before (writing codes in Verilog then compile them blah blah blah..). But I am very clueless about how to modify the lower level units by myself!

--- Quote End ---

From a code perspective you might have to write multiple assignments in order to get enough delay for whaterver your purposes are.

delayed_sig(i) <= delay_sig(i-1);

delayed_sig(0) <= input_sig;

And then use the proper attribute to inhibit logic optimization.

--- Quote Start ---

so here is my question:

How to modify the bottom level elements of FPGA by myself?

Is there any Altera tool that allows me to do so?

--- Quote End ---

Quartus will allow you to specify locations.

Kevin Jennings