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I am a student and recently my professor ask me to see if it is possible to create delay lines with FPGA ( by cascading buffers or inverters together ) so that we may be able to test chip delays with such a tool.
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Yes it is, but the stability of the delay might not be acceptable. The delay will be a function of the fabrication process, the supply voltage and the local die temperature.
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which means that I need to modify those gates inside a FPGA directly and somehow arrange them together to generate different delays.
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That's correct, you will likely need to hand pick locations.
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I do have experience of programming FPGA with altera tools before (writing codes in Verilog then compile them blah blah blah..). But I am very clueless about how to modify the lower level units by myself!
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From a code perspective you might have to write multiple assignments in order to get enough delay for whaterver your purposes are.
delayed_sig(i) <= delay_sig(i-1);
delayed_sig(0) <= input_sig;
And then use the proper attribute to inhibit logic optimization.
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so here is my question:
How to modify the bottom level elements of FPGA by myself?
Is there any Altera tool that allows me to do so?
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Quartus will allow you to specify locations.
Kevin Jennings
Honored Contributor
