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Altera_Forum
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14 years ago

Is it possible to make a bottom level design

Hi all! I am a student and recently my professor ask me to see if it is possible to create delay lines with FPGA ( by cascading buffers or inverters together ) so that we may be able to test ch...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

There are no gates inside a FPGA which can be re-arranjed.

There are just logic elements which can be programmed in different ways.

If you want to create delay lines, you can use use LCELL or CARRY primitive.

You can also use a family specific primitive, such as "cycloneiii_lcell_comb", but the above ones should be good enough.