Is it possible to feed a MAX10 PLL with slow clock input (< 5MHz)?

Max 10 datasheet indicates absolute minimum frequency input to the PLL is 5MHz.

Ref datasheet timing / electrical specs, page 26:

PLL Specifications
Table 27. PLL Specifications for MAX 10 Devices
VCCD_PLL should always be connected to VCCINT through decoupling capacitor and ferrite bead.
Symbol  Parameter                Condition   Min   Typ    Max    Unit
 fIN    Input clock frequency        —        5     —    472.5   MHz

If you could 2X the frequency to ~7.2MHz it would be in range. So something simple like this externally:

https://www.maximintegrated.com/en/app-notes/index.mvp/id/3327

would work.

Or, use something like a 14.31818MHz oscillator to feed into your FPGA, and multiply up from that. And divide this frequency down by four to feed to your external logic that requires 3.58...MHz to operate. Of course this assumes you can replace the 3.58MHz signal source with another source (may not be possible, depends on your external circuitry).