Is it possible to connect two ethernet DE2-115 PHY chips back to back?

Phy's usually could also work fine without configuring via the Management Interface (MDIO). Make sure the bootstrap Options are set correct and the Phy has a proper Reset. The Board supports also RGMII, make sure the Jumper is set to MII.

In your code the RX and TX Clocks are unused, this can't work.

In MII Mode the TX CLK is coming from the Phy for the TX Data to the Phy. This is the same CLK as the Board CLK, but not in phase. The RX CLK is a derived CLK from your PC. These are different clocks!

To try your loopback you need a FIFO (about +-4 nibbles) from the RX DATA @ RX Clk to the TX DATA @ TX Clk.

Also make sure that you meet timing requrements (tsu, th) to the Phys. I have never done a simple Phy loopback, but do not see why this shouldn't work (with fifo, correct IO timing, and correct bootstrap options).