Is it possible to connect two ethernet DE2-115 PHY chips back to back?

I played a bit with my DE2 some time ago mostly with the Ethernet chip (built a UDP send and receive with a PC). From what i know what you are trying to do requires advanced knowledge. The PHY needs some initializations and some clock signals to get going. The MII also needs a kind of master and the PHY is rather a slave than a master, so a simple connection between the 2 without some intelligence behind it will not work.

There is however a TSE tutorial available from Altera and this tutorial is a start to do what you are trying to do: 1 PHY receives the other one sends. It could be a good place to start your project. (TSE = triple speed Ethernet).

Best Regards,

Johi.

ftp://ftp.altera.com/up/pub/altera_material/12.0/tutorials/de2-115/using_triple_speed_ethernet.pdf

(If you start experimenting with the tutorial make sure you have the one for Your version of Quartus.)

Edit:

After reading the reply from DUSTERBERG, i think he/she has a point, but this depends from what you define as "possible" and "not possible". In many practical applications the PHY's are controlled by a Nios configuration (a CPU). PHY, CPU, ram and other components are connected together with Verilog/VHDL code.

Hence it should be possible to do, based on advanced knowledge. Point of attention is that the datasheet from the PHY from the DE2 requires that you sign a NDA (non disclosure agreement) with the supplier. Therefore I rephrased the above post from not possible to advanced knowledge. Based on the nature of your question I assumed that you do not have this knowledge.

If you really want to go this want go this way. You will have to manage different things, for example: the negotiation of the baud rate between router and DE-PHY and PC and other DE-PHY should end up with the same baud rate (or you will have to fix the rate yourselves) or you will have to install frame buffers. You will need to provide clocks with the correct baud rates, you will also have to set registers with the correct values.

My advice remains the same: not the way to go unless you have advanced knowledge.

Phy's usually could also work fine without configuring via the Management Interface (MDIO). Make sure the bootstrap Options are set correct and the Phy has a proper Reset. The Board supports also RGMII, make sure the Jumper is set to MII.

In your code the RX and TX Clocks are unused, this can't work.

In MII Mode the TX CLK is coming from the Phy for the TX Data to the Phy. This is the same CLK as the Board CLK, but not in phase. The RX CLK is a derived CLK from your PC. These are different clocks!

To try your loopback you need a FIFO (about +-4 nibbles) from the RX DATA @ RX Clk to the TX DATA @ TX Clk.

Also make sure that you meet timing requrements (tsu, th) to the Phys. I have never done a simple Phy loopback, but do not see why this shouldn't work (with fifo, correct IO timing, and correct bootstrap options).

Thanks all for replying,

At first, I thought that would be possible because I read a similar question in another forum (with different PHY chip) [link here] (https://e2e.ti.com/support/interface/ethernet/f/903/t/294643#pi239031350filter=all&pi239031350scroll=false). I also used the document showing PHY-to-PHY MII connection.

I don't know if my code didn't work because different PHY chip behaves differently, or I misunderstood MII interface. After reading the replies now I think I should learn how to write some codes to configure these two PHY chips correctly.

Actually my goal is to tap MII interface and encode it with manchester coding (as per IEEE ethernet standard) for learning purpose.