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Jens's avatar
Jens
Icon for Occasional Contributor rankOccasional Contributor
5 years ago

Is it not possible to use all clock outputs of an Arria 10 IOPLL

I'm using the 10AX048H4F34E3SG device with 130 LVDS data pairs connected. The LVDS pins are distributed over 6 IO-banks. All pins feed to a GPIO primitive (ddr mode). The clock for the GPIO comes fr...
sstrell's avatar
sstrell
Icon for Super Contributor rankSuper Contributor
5 years ago

The tool is only showing you the clock that could not be routed. You probably need to take more clocks off of the global routing channels to free up resource usage. Check the Compilation Report to see which clocks (or potentially high fanout control signals) are using the global clocks and see if you can remove more of them.

I'm not sure why turning off the Auto Global setting causes the same issue, but turning that off means that you would need to manually specify which clocks should use the global routing channels.

Jens's avatar
Jens
Icon for Occasional Contributor rankOccasional Contributor
5 years ago

I checked the report (congestion summary in Fitter report) and tried to remove all clocks.
But the error remains. It seems the fitter do not recognize my assignments.

assignment:
-name GLOBAL_SIGNAL OFF -to "deserializer:DESER|sen_pll:SENPLL_6|sen_pll_altera_iopll_181_qprrpya:iopll_0|altera_iopll:altera_iopll_i|twentynm_iopll_ip:twentynm_pll|outclk[3]~CLKENA0"

fitter:
Info (175026): Source: auto-promoted clock driver deserializer:DESER|sen_pll:SENPLL_6|sen_pll_altera_iopll_181_qprrpya:iopll_0|altera_iopll:altera_iopll_i|twentynm_iopll_ip:twentynm_pll|outclk[3]~CLKENA0

What can I do more?

  • EngWei_O_Intel's avatar
    EngWei_O_Intel
    Icon for Frequent Contributor rankFrequent Contributor
    5 years ago

    Hi Jen

    Are you able to share you sample design?

    Thanks.

    Eng Wei

    • EngWei_O_Intel's avatar
      EngWei_O_Intel
      Icon for Frequent Contributor rankFrequent Contributor
      5 years ago

      Hi Jen

      Have you try to use ALTCLKCTRL IP to route your clock to regional clock?

      Thanks.

      Eng Wei

      • Jens's avatar
        Jens
        Icon for Occasional Contributor rankOccasional Contributor
        5 years ago

        Hi Eng Wei,

        no. It seems to me that Quartus have no problem to route the global clock to regional clock. But there are not enough ressorces to connect all PLL outputs in that region.

        Jens

    • Jens's avatar
      Jens
      Icon for Occasional Contributor rankOccasional Contributor
      5 years ago

      Hi Eng Wei

      I made a stripped down version of this project so you can check the quartus errors.

      Jens