Is it not possible to use all clock outputs of an Arria 10 IOPLL

I'm using the 10AX048H4F34E3SG device with 130 LVDS data pairs connected. The LVDS pins are distributed over 6 IO-banks.
All pins feed to a GPIO primitive (ddr mode). The clock for the GPIO comes from the PLL in the same IO-bank. For a group of signals I want use 8 clock outputs of that PLL for a dynamic phase shift.
To realize phase shift for all 130 pins I want to use 34 different clocks which feeds the full rate clock input of the GPIO.

During fit Quartus produce some errors:
The Fitter cannot place 1 auto-promoted clock driver, which is within IOPLL Intel FPGA IP sen_pll_altera_iopll_181_qprrpya
Error (177032): Section clock (SCLK) network in spine clock region bounded by (109,0) and (148,31) is congested due to limited connectivity

Info (18630): This congestion may be avoided by moving or disabling promotion of any of the following competing signals:
Info (175030): Unroutable signal:
Info (175026): Source: auto-promoted clock driver deserializer:DESER|sen_pll:SENPLL_3|sen_pll_altera_iopll_181_qprrpya:iopll_0|altera_iopll:altera_iopll_i|twentynm_iopll_ip:twentynm_pll|outclk[2]~CLKENA0

I have done a second run with that constraint:
set_instance_assignment -name GLOBAL_SIGNAL OFF -to "deserializer:DESER|sen_pll:SENPLL_3|sen_pll_altera_iopll_181_qprrpya:iopll_0|altera_iopll:altera_iopll_i|twentynm_iopll_ip:twentynm_pll|outclk[2]~CLKENA0

But there is no effect. The error remains. I also tried to switch off the Auto Global Clock option in the dvanced Fitter Settings but the error remains.

Why is it not possible to use all clock outputs of a PLL? When I reduce the number of clocks than fitting is successfully.

Jens