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Altera_Forum
Honored Contributor
14 years agoI guess you are asking a way to expose the separate signals out of the Qsys block.
If this is not mandatory, you can easily do the same externally with the following VHDL assignments. You have, for example Qsys_conduit : std_logic_vector(3 downto 0); So, you define: signal_to_device0 <= Qsys_conduit(0); signal_to_device1 <= Qsys_conduit(1); signal_to_device2 <= Qsys_conduit(2); signal_to_device3 <= Qsys_conduit(3);