Altera_Forum
Honored Contributor
Honored ContributorIs HardCopy obsolete?
Is HardCopy obsolete? What's the strategy of Altera to port from FPGA to ASIC?
Forum Discussion
5 Replies
Altera_ForumI know they are not supporting Hardcopy/Hardcopy II in the latest quartus, but I think you need to talk to your FAE if they are still supporting new designs.
I've done a Hardcopy design in the past. It's pretty much a standard ASIC flow. with only a nebulous guarantee that if you met timing in the FPGA, it would meet timing in the Hardcopy ASIC. There was still remapping issues with PLL's that had to be dealt with. Altera IP's (Like NIOS) were cheaper/easier in a Hardcopy. But you can do it in a standard ASIC as well. If you are looking for help in an FPGA->ASIC migration, I can help. Pete- Altera_Forum
For now it is just to know since in Quartus I don't see anymore Hardcopy..
Thank you - Altera_Forum
- Altera_Forum
So for new design starts Xilinx is the way for going to structured ASIC?
- Altera_Forum
I haven't done an easy path migration, So I can't really comment on it. But from my experience with Hardcopy, the time and effort involved with the FPGA -> Hardcopy transition was almost the same as the time and effort involved with a FPGA -> Standard Cell ASIC. The NRE was lower than the hardcopy process native costs, but was higher than the NRE for a larger geometry process NRE that the design could fit in and still meet timing.
To me it never made much sense, primarily because the advantage in cost wasn't really there and the advantage in the memory and PLL's being exactly the same as the FPGA wasn't really there either. If you are sub 10k per year, keep it in FPGA. if you are > 200k per year, go ASIC. if you are in the zone of 10k to 200k per year, you really have to look at the NRE and part costs and balance the return on investment. For a moment in time eASIC provided a solution for < 50k that was great for this region, but now their pricing is much closer to a ASIC NRE as well. Pete
