Is HardCopy obsolete?

I know they are not supporting Hardcopy/Hardcopy II in the latest quartus, but I think you need to talk to your FAE if they are still supporting new designs.

I've done a Hardcopy design in the past. It's pretty much a standard ASIC flow. with only a nebulous guarantee that if you met timing in the FPGA, it would meet timing in the Hardcopy ASIC.

There was still remapping issues with PLL's that had to be dealt with. Altera IP's (Like NIOS) were cheaper/easier in a Hardcopy. But you can do it in a standard ASIC as well.

If you are looking for help in an FPGA->ASIC migration, I can help.

Pete