Forum Discussion
TNaka61
New Contributor
New ContributorIs "Cyclone 10 LP" slower than "Cyclone IV E" ?
I tested according to the same source code (VHDL) shown below. The reported delay was almost the same... but "Cyclone 10 LP" gave the following timing error @300MHz clock. Is my setting incomplete...
KennyT_altera
Super Contributor
Super Contributorhttps://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_altera_phylite.pdf
The IP core has a dedicated PHY clock tree in each I/O bank. The PHY clock tree is shorter which yields lower jitter and duty cycle distortion (DCD), enabling designs to achieve higher performance.
