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KennyT_altera
Super Contributor
6 years agohttps://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_altera_phylite.pdf
The IP core has a dedicated PHY clock tree in each I/O bank. The PHY clock tree is shorter which yields lower jitter and duty cycle distortion (DCD), enabling designs to achieve higher performance.