Forum Discussion
Thankyou for fast responce ... but,
I made a supplementary test with a FF in an IO pad that is non-DDIO.
so, I found that the speed was virtually the same as shown below.
DEVICE:10CL006YU256C8G (Cyclone 10 LP)
; Slow 1200mV 85C Model Fmax Summary ;
+------------+-----------------+------------------------------------------------+------------------------------------------------+
; Fmax ; Restricted Fmax ; Clock Name ; Note ;
+------------+-----------------+------------------------------------------------+------------------------------------------------+
; 656.17 MHz ; 402.09 MHz ; pl|altpll_component|auto_generated|pll1|clk[0] ; limit due to minimum period restriction (tmin) ;
DEVICE:EP4CE6F17C8 (Cyclone IV E)
; Slow 1200mV 85C Model Fmax Summary ;
+-----------+-----------------+------------------------------------------------+------------------------------------------------+
; Fmax ; Restricted Fmax ; Clock Name ; Note ;
+-----------+-----------------+------------------------------------------------+------------------------------------------------+
; 656.6 MHz ; 402.09 MHz ; pl|altpll_component|auto_generated|pll1|clk[0] ; limit due to minimum period restriction (tmin) ;
From this result, it can be seen that only "Cyclone 10 LP"'s DDIO is about half the speed of non-DDIO,
and "Cyclone IV E"'s DDIO and non-DDIO are almost the same speed.
However, for both devices, the 0.5 cycle time is shorter than the Tco of DDIO output.
Therefore, the shortest pulse may disappear, but a long pulse should provide 0.5 cycle time resolution of the edge.
Is there a problem with my research method?
or Is either wrong?