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Altera_Forum's avatar
Altera_Forum
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8 years ago

Is CPLD required for booting CYCLONE 5 FPGA from QSPI flash.

in cyclone 5- fpga can’t able to fetch the program from spi flash

FPGA - cyclone 5 (5cgtfd7d5f27i7n)

SPI FLASH - epcq128si16n

in our board only one spi flash (configuration flash) is there which is connected to dedicated pins of fpga,no cpld ,no other flash is there.

1. I have created LED program in quartux2, generated .sof file, and programmed it in to FPGA its working the LED’s are blinking and CONFIG_DONE LED also glowing.

2. I converted .sof to .jic, and programmed to SPI flash, it IS successfully programmed .It means that program is successfully written on SPI FLASH.

3. While I press reset button(making fpga_nconfig low), than LED not blinking, CONFIG DONE LED also not glowing it means that FPGA is not able to fetch the program from SPI FLASH.

same process i tried in two evaluation board as given below it is working -

I tried .JIC method on cyclone5 GT evaluation board and cyclone5 Gx .

In this board FPGA is booting from SPI flash after Power ON.

In both evaluation board CPLD is also in between FPGA and QSPI flash.

In our custum board CPLD is not used between FPGA and QSPI flash.

Is CPLD required for booting FPGA from flash or not ?

IN two board we have seen that .JIC is working ,in both board CPLD is there.

So my doubt is without CPLD it may be .jic process will not work , if some other process is there than you tell me that procedure through NIOS2 ,I will try that procedure in our board.

THANKS & REGARDS

Deepak kumar

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  • Altera_Forum's avatar
    Altera_Forum
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    8 years ago

    --- Quote Start ---

    I presume that the power supply have tens to hundreds of microseconds rise time each, thus specifying nanosecond delays is meaningless respectively erroneous.

    Expected power-up sequence is clearly specified in the Quartus device handbook. Read it.

    --- Quote End ---

    Hi,

    sorry,power supply has rise time in milliseconds only ,By mistake i kept ns in excel sheet i updated and attached it.

    I gone through the datasheet and i attached my doubt in that datasheet page .

    Thanks & Regards

    DEEPAK
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    8 years ago

    Your power up sequence looks OK. Refer to the 'Power-Up Sequence Recommendation for Cyclone V Devices' section, page 10-4, of the 'cyclone v device handbook (https://www.altera.com/en_us/pdfs/literature/hb/cyclone-v/cv_5v2.pdf)'. Note the comments about monotonicity and meeting the T_ramp time.

    Also consider the 'Power Pin Connections' section, page 12, of the 'arria v and cyclone v design guidelines (https://www.altera.com/en_us/pdfs/literature/an/an662.pdf)'.

    --- Quote Start ---

    ...ensure that the minimum current requirement for the power-on-reset (POR) supplies is available during device power up.

    --- Quote End ---

    Are your power supplies good enough for this? Note the maximum currents required in Table 10-1: "Maximum Power Supply Current Transient and Typical Duration", in the Device Handbook. If the supplies dip at all during power up the device may not start properly.

    Are ALL you device's power pins connected? Do you have a schematic/symbol/footprint issue?

    I'm suspecting this is power related.

    Cheers,

    Alex