Forum Discussion
Altera_Forum
Honored Contributor
12 years agoOkay, it would appear that the option works as expected. I created a JIC file from the SOF and checked the "Disable AS mode CONF_DONE error check" box. Programmed the EPCS64 with the JIC and the FPGA configured correctly at power up. Hurrah.
Here's where I'm stuck now. I normally create the EPCS image with sof2flash followed by elf2flash with the --after option. The programming file converter will generate lots of useful files, but not a srec flash file. Looking at what sof2flash does with the --verbose flag, it generates a POF from the SOF with quartus_cpf and then generates a RPD from the POF with quartus_cpf. Then the info spewed out by --verbose stops. What is the step to create a flash SREC file from the RPD? Thanks, Mark.