Honored ContributorHi,
I work on cyclone IV FPGA with Quartus 10.1 I have an IP which behaves differently in every starting up of the FPGA. Is there a safe way of configuring the fpga (with mode erase all of memories and registers)? or is there any option to activate before compilation? Could someone help me NB: I have initialised every signal and every ram Thanks
Honored ContributorEither Your design doesn't meet timing constrains or the FPGA is broken.
Honored Contributortake a look at reset logic, maybe add some synchronizes
Honored Contributorthank you for your reply,
All timing constrains are met and the FPGA is not still broken. I hope, it is something like the reply of "thepancake"Honored ContributorAre You sure You are not generating any metastability sources? E.g. async inputs?
Honored ContributorI have checked Mestability report of timeQuest Analyzer but all values are correct
Honored ContributorHi everyone,
I resolve the problem by clearing all RAM and FIFO at power-up reset! thx
