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Altera_Forum
Honored Contributor
Honored ContributorIP starting up stability
Hi,
I work on cyclone IV FPGA with Quartus 10.1 I have an IP which behaves differently in every starting up of the FPGA. Is there a safe way of configuring the fpga (with mode erase all of memories and registers)? or is there any option to activate before compilation? Could someone help me NB: I have initialised every signal and every ram Thanks6 Replies
Altera_ForumHi everyone,
I resolve the problem by clearing all RAM and FIFO at power-up reset! thx- Altera_Forum
I have checked Mestability report of timeQuest Analyzer but all values are correct
- Altera_Forum
Are You sure You are not generating any metastability sources? E.g. async inputs?
- Altera_Forum
thank you for your reply,
All timing constrains are met and the FPGA is not still broken. I hope, it is something like the reply of "thepancake" - Altera_Forum
take a look at reset logic, maybe add some synchronizes
- Altera_Forum
Either Your design doesn't meet timing constrains or the FPGA is broken.
