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Altera_Forum's avatar
Altera_Forum
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15 years ago

IP starting up stability

Hi, I work on cyclone IV FPGA with Quartus 10.1 I have an IP which behaves differently in every starting up of the FPGA. Is there a safe way of configuring the fpga (with mode erase a...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Either Your design doesn't meet timing constrains or the FPGA is broken.