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testp
New Contributor
New ContributorIP optimized protection
I want to use CYCLONE5 to create 3 PLLs and connect each PLL output to an external pin. I created three PLLs with PLL Intel FPGA IP from the IP Catalog.
When implemented, only one PLL is assigned ...
SyafieqS
Super Contributor
Super ContributorHi,
have you try the keep and preserve attribute? This will keep the register from optimized, you have to modify this in HDL
