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testp's avatar
testp
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5 years ago

IP optimized protection

I want to use CYCLONE5 to create 3 PLLs and connect each PLL output to an external pin. I created three PLLs with PLL Intel FPGA IP from the IP Catalog. When implemented, only one PLL is assigned ...
sstrell's avatar
sstrell
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5 years ago

Is there a reason why you need 3 PLLs for this? If the 3 output clocks used 3 different input reference clocks, the tool would not optimize like this.

  • testp's avatar
    testp
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    5 years ago

    Thank you for your reply.

    Sorry for the lack of explanation.

    The circuit configuration is as follows.

    It seems that three PLLs are recognized in the synthesis,
    The Fitter optimizes the PLL to one.
    Therefore, I think that there is no problem with the instance method and description.
    My guess is that some option settings are missing.

    <FPGA external pin>
    input CLKIN;

    out put PLLA_CLKOUT [3: 0];
    out put PLLB_CLKOUT [3: 0];
    out put PLLC_CLKOUT [3: 0];

    <PLL instance>
    pllA pllA (
    .rst (rst),
    .refclk (CLKIN),
    .outclk_0 (PLLA_CLKOUT [0]),
    .outclk_1 (PLLA_CLKOUT [1]),
    .outclk_2 (PLLA_CLKOUT [2]),
    .outclk_3 (PLLA_CLKOUT [3]),
    .locked ()
    );


    pllB pllB (
    .rst (rst),
    .refclk (CLKIN),
    .outclk_0 (PLLB_CLKOUT [0]),
    .outclk_1 (PLLB_CLKOUT [1]),
    .outclk_2 (PLLB_CLKOUT [2]),
    .outclk_3 (PLLB_CLKOUT [3]),
    .locked ()
    );


    pllC pllC (
    .rst (rst),
    .refclk (CLKIN),
    .outclk_0 (PLLC_CLKOUT [0]),
    .outclk_1 (PLLC_CLKOUT [1]),
    .outclk_2 (PLLC_CLKOUT [2]),
    .outclk_3 (PLLC_CLKOUT [3]),
    .locked ()
    );


    <PLL setting>
    No phase adjustment
    pll input: 100MHz
    pll Each output: 100MHz
    All pllA to C have the same conditions
    * I would like to use 3 PLLs for 3 groups and supply 4 CLKs.
    * Since it is a trial, the pll setting is tentative and all have the same parameters.
    * IP settings other than the above are left at their defaults.


    I would appreciate any advice.
    Thanking you in advance.

    • sstrell's avatar
      sstrell
      Icon for Super Contributor rankSuper Contributor
      5 years ago

      So you have 12 output clocks, 4 from each PLL. Are all these clocks connected to logic in your design? If not, the tool will optimize them away.

      • testp's avatar
        testp
        Icon for New Contributor rankNew Contributor
        5 years ago

        The 12 output CLKs are not used in the logic inside the FPGA.
        Connect directly from the PLL output to the FPGA external pin.

        As an example, it is not processed inside the FPGA,
        It is simply a configuration that distributes one CLK input from the outside to the FPGA external pin using a PLL.
        Since there are three types of external devices, we are considering using one PLL for each external device.
        I would like to use a total of 3 PLLs and supply each CLK.

        The tool is said to be optimized if it is not connected to the logic inside the FPGA,
        Can I change the settings of the tool so that it is not optimized?