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Altera_Forum
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15 years ago

I/O standard:Different between 3.3V and 2.5V

Hi,

In my hardware, I/O standard of most of the ICs connected to CycloneIII are 3.3V, but it also need LVDS connected to CycloneIII.

It should to set the voltage of the bank to 2.5V which include LVDS according to the rule of the QuartusII.

If power the bank with 3.3V, but set the I/O standard to 2.5v in QuartusII, does it mater?

Thanks

7 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    --- Quote Start ---

    If power the bank with 3.3V, but set the I/O standard to 2.5v in QuartusII, does it mater?

    --- Quote End ---

    Yes, the LVDS I/Os are not guaranteed to work at this voltage. Possibly they can with reduce performance, but you can't rely on it, the operation is beyond the specifications.
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    If your LVDS signals are input-only to the FPGA, then its possible that you can use a 3.3V bank. If the LVDS signals are going to LVDS receivers or clock input pins, then it might be acceptable. Use Quartus to setup a design and make sure to assign 3.3V I/Os and the LVDS inputs and then attempt P&R. Quartus will warn about invalid assignments.

    If you require LVDS outputs, then the LVDS drivers will only work with 2.5V VCCIO.

    If you do need drivers, and they do not need to operate at high-speed, then you might be able to use external resistor networks on pairs of 3.3V signal drivers to get LVDS compatible output voltages (though I've usually seen that done with a 2.5V VCCIO too). Another option is to use an external 3.3V-to-LVDS buffer; National semiconductor has plenty of parts.

    Cheers,

    Dave
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    Hey...

    According to recent posts.. If i supply I/O bank with 3.3 V, is it possible to use LVDS (input only, inclusive clock signal) standard at this bank or do i´ve to supply with 2.5V ?? already some results available ??

    thanks for help

    greets
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    Hi,

    as far as I understand the Cyclone III spec. and the Application Note 447 you can connect 3.3V LVTTL/LVCMOS devices to a 2.5 cyclone III I/O bank. So you can power the LVDS bank with 2.5V and connect the other I/Os of this bank to your external 3.3V devices. You should use series termination for all pins which are driven from your external 3.3 devices to your 2.5V I/O bank and you should disable the clamping diode for the input signals in this bank.
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    I would not recommend it. The spec. is clear. Vccio max for LVDS is 2.625V. For a long term reliable operation you should keep all values within the spec.

  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    ok, you´re right, specifications are clear and i should hold them... thanks for your help !!