Honored Contributor
Honored ContributorIf your LVDS signals are input-only to the FPGA, then its possible that you can use a 3.3V bank. If the LVDS signals are going to LVDS receivers or clock input pins, then it might be acceptable. Use Quartus to setup a design and make sure to assign 3.3V I/Os and the LVDS inputs and then attempt P&R. Quartus will warn about invalid assignments.
If you require LVDS outputs, then the LVDS drivers will only work with 2.5V VCCIO. If you do need drivers, and they do not need to operate at high-speed, then you might be able to use external resistor networks on pairs of 3.3V signal drivers to get LVDS compatible output voltages (though I've usually seen that done with a 2.5V VCCIO too). Another option is to use an external 3.3V-to-LVDS buffer; National semiconductor has plenty of parts. Cheers, Dave
