Forum Discussion
Occasional ContributorIO_OBUF Placement and IC delay in timing path
Is there anyways we can constrain the placement of IO_OBUF so that it is closer to the pad.
How can we reduce the IC delay in the timing path?
17 Replies
KennyT_alteraSuper Contributor
Any Update?
- KennyT_altera
can u share the screenshot?
1) the resource property editor that show that the register is inside the DDIO location?
2) Timing analyzer report showing the violation
3) the latest .sdc files showing how frequency that you use for that pin
4) what IO standard that you are using
- KennyT_altera
any update?
SK_VAI am still not able to meet the timing with the suggested options.When I add additional registers,the interface itself is not working.
6.105 is not IC delay its cell delay.
- KennyT_altera
can u send out the same screenshot?
- SK_VA
Hi,
I tried this solution by registering the output.But timing is still failing.
- SK_VA
Thanks for reply. nand_dq_out is bidirectional.Let me try adding register.
- KennyT_altera
You misunderstood how to use the fast input and fast output register. Those have to be points towards the register, base on your screenshot, you have to apply to address_latch. However, even if you apply to it, it will not work because you have a nand_dq_out in btw the IO. I suggest you manually add another register after the nand_dq_out and apply the fast output register.
sstrell6.105? Where exactly are you seeing that? That's huge. Can you show your .sdc and the full data path report in that screenshot (Data Arrival and Data Required paths)?
#iwork4intel
- KennyT_altera
How about show me the screenshot on where you have set the setting and the resource property editor?
- SK_VA
Hi,
Sorry,I cannot share the qar file of the project.
