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IDeyn's avatar
IDeyn
Icon for Contributor rankContributor
7 years ago

I/O D1/D3 delay values higher than needed.

I have a problem, and it could be described like this: there is PHY - to FPGA (Cyclone V) RGMII interface, receive side (for FPGA). Namely I have 125 MHZ, DDR, I use center-aligned mode, I exploi...
AnandRaj_S_Intel's avatar
AnandRaj_S_Intel
Icon for Regular Contributor rankRegular Contributor
7 years ago

Hi Ivan,

That's how tool behaves.

Design may/may not meet timing requirements. We have to set it manually.

Regards

Anand

  • IDeyn's avatar
    IDeyn
    Icon for Contributor rankContributor
    7 years ago

    Hi Anand!

    Sorry for my persistence, but if it is like you said, what is the driving signal for the engine to automatically set I/O delay elements values?

    I mean, the engine should be guided by something, so why not to be guided by a positive slack as an aim?

    Because it explicitly does not set them randomly, as we demonstrated the timing results are quite stable.

    --

    Best regards,

    Ivan