Forum Discussion

IDeyn's avatar
IDeyn
Icon for Contributor rankContributor
6 years ago

I/O D1/D3 delay values higher than needed.

I have a problem, and it could be described like this: there is PHY - to FPGA (Cyclone V) RGMII interface, receive side (for FPGA). Namely I have 125 MHZ, DDR, I use center-aligned mode, I exploi...
AnandRaj_S_Intel's avatar
AnandRaj_S_Intel
Icon for Regular Contributor rankRegular Contributor
6 years ago

Hi Ivan,

May be due to constraints.

we need to have tight, complete and accurate timing constraints.

Regards

Anand