Forum Discussion
IDeyn
Contributor
ContributorI/O D1/D3 delay values higher than needed.
I have a problem, and it could be described like this: there is PHY - to FPGA (Cyclone V) RGMII interface, receive side (for FPGA). Namely I have 125 MHZ, DDR, I use center-aligned mode, I exploi...
AnandRaj_S_Intel
Regular Contributor
Regular ContributorHi Ivan,
May be due to constraints.
we need to have tight, complete and accurate timing constraints.
Regards
Anand
