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IDeyn's avatar
IDeyn
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7 years ago

I/O D1/D3 delay values higher than needed.

I have a problem, and it could be described like this: there is PHY - to FPGA (Cyclone V) RGMII interface, receive side (for FPGA). Namely I have 125 MHZ, DDR, I use center-aligned mode, I exploi...
IDeyn's avatar
IDeyn
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7 years ago

Hi Anand.

My internal registers are located in Fast I\O, they are part of TSE IP Core and it puts them into Fast I\O automatically.

So the paths are totally fixed.

I will try to create a simple project and if the problem will still be present I will attach it here.

Thank you.

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Best regards,

Ivan

IDeyn's avatar
IDeyn
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7 years ago

Hi Anand.

For now, what have I done.

New simple project with TSE was created, and it works fine, I/O delays are chosen by the software correctly and timing meets with positive slacks on both setup and hold.

It's strange because TSE I/O timing is independent from other design parts - because it is I/O timing.

But in the full version of the project I still observe wrong values, and I noticed an interesting thing - choosing Quartus 16.0, I acquired better performance -

for example RXD1 Slack changed from -0.613 to -0.202. I had compared fitter settings (16.0 vs 17.1) and hadn't found any differences there.

So for now I can say that it looks like the issue which is located deep inside the engine and depends on version of Quartus.

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Best regards,

Ivan