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IDeyn's avatar
IDeyn
Icon for Contributor rankContributor
7 years ago

I/O D1/D3 delay values higher than needed.

I have a problem, and it could be described like this: there is PHY - to FPGA (Cyclone V) RGMII interface, receive side (for FPGA). Namely I have 125 MHZ, DDR, I use center-aligned mode, I exploi...
IDeyn's avatar
IDeyn
Icon for Contributor rankContributor
7 years ago

Hi Anand.

My internal registers are located in Fast I\O, they are part of TSE IP Core and it puts them into Fast I\O automatically.

So the paths are totally fixed.

I will try to create a simple project and if the problem will still be present I will attach it here.

Thank you.

--

Best regards,

Ivan

AnandRaj_S_Intel's avatar
AnandRaj_S_Intel
Icon for Regular Contributor rankRegular Contributor
7 years ago

Okay, Thanks for update.

Regards

Anand