mnasser431998
New Contributor
New ContributorIO banks voltages
Hello everyone,
I have a simple question about IO banks voltages from PCB design point of view. I noticed that DDR memories work SSTL IO standard which is about 1.2V and I know that I can change I...
You need to follow the pin connection guidelines document for your selected device family, for example Cyclone 10 GX:
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/dp/cyclone-10/pcg-01022.pdf
What's nice about an FPGA is that you can create the design in Quartus, choosing the voltages and standards you need, and the resulting compilation information will help in setting up how to power your device in hardware.
