Invalid logic levels at output of FPGA

Your problem is you have your timer free running and not based on clock.

You have mixed your state machine logic and other logic together.. And have the timer addition happening regardless in a combinational block instead of a clock based always block.

so in simulation the timer is just free running and zero time is moving forward, thus the "Hang" you are experiencing.

On the hardware, the timer is running like mad at the highest combinational frequency that is possible, so the output looks like a sign wave because it's toggling faster than the output can really reach.

Isolate the statemachine case from the logic case, and move the logic case into a always@(posedge clk) block and you should be closer.

Pete