T = 20ns (50MHz)
So one second would be 1 000 000 000ns / 20ns = 50 000 000 clock cycles. You could use a free running modulo counter that starts at 0 and counts up to 49 999 999 before rolling back to 0. Then just compare the output of the counter with 49 999 999 and when the comparison is true enable a register (SR flip flop). When the CPU services the interrupt you would clear this same register so that you will be alerted by interrupt the next time the counter hits 49 999 999. This is practically how the timer peripheral in SOPC Builder and Qsys works.