Honored Contributor
Honored ContributorAltera FPGAs have no separate series termination resistors for SSTL I/O standards, all OCT (on-chip termination) schemes are achieved by activating a combination of output transistors. In so far, series termination is just another name for current strength. You can calculate the effective series termination yourself from the respective IBIS files, that tabulate output characteristics for all I/O standards.
For most FPGAs, a 50 ohm series termination with SSTL class I and 25 ohm with class II is given, see e.g. Table 1 in AN408. There seems to be some confusion however with Cyclone II, the above schema shows 25 ohm for both standards, while the datasheet text tells about 50 ohm series OCT in one place and 8 versus 16 mA current strength in another. Clearly, 8 mA involves a different effective series impedance than 16 mA. As in the AN408 examples, choosing 16 mA respectively 25 ohm with SSTL class I can result in a better signal quality and higher error-free memory clock frequency in some applications. It's good to follow the general sugggestion in a first step and check optimal settings for the individual system later.
