Internal Clock HELP

a cascade of counters, something like this:

process -- clked on 27MHz
if Hz_count /= 27000000-1 then
    Hz_count <= Hz_count +1;
else
     Hz_count <= 0;
     if seconds_count /= 59 then
             seconds_count <= seconds_count + 1;
     else
             seconds_count <= 0;
             if minutes_count /= 59 then
                   minutes_count <= minutes_count + 1;
              else
                   minute_count <= 0;
                   if hours_count /= 23 then
                          hours_count <= hours_count + 1;
                   else
                          hours_count <= 0;
                          if days_count /= final_day then
                                 days_count <= days_count + 1;
                          else
                                  days_count <= 1;
                          end if;
                  end if;
            end if;
     end if;
end if;

Is this pure 100% HDL project OR Nios II project?

It's a pure VHDL .. usually i used to divide the clock to make it faster.. but now i need it slower ..

Then as suggested by others, previous posts, you can divide down MHz to Hz. Then use it has global clock. At Hz frequency, PLL would not work.