Honored Contributor
Honored ContributorI'm pretty convinced your device is configuring successfully. Your suggestion that it's partial is understandable but not likely. Check the 'CONF_DONE' pin on the device if you're in any doubt. Assuming the design pulls this high with a resistor (as recommended in the design docs), it will go 'high' - to whatever voltage the resistor pulls it to - when the device is configured.
I'm more concerned about a handling issue or excessive loads placed directly on FPGA pins configured as output signals, resulting in blown buffers on certain I/O pins. This I have seen on several device families including Cyclone III. I hope that latter (excessive loading) has been thoroughly considered and that the loading on 'sclk' is appropriate. I agree with gj_leeson too. You need to consider the power supply behaviour, particularly at power up. From the design docs for this family: --- Quote Start --- You can power up or power down the VCCIO, VCCA, and VCCINT pins in any sequence. The VCCIO, VCCA, and VCCINT must have monotonic rise to their steady state levels. The maximum power ramp rate for fast POR time is 3 ms, and 50 ms for standard POR time, respectively. The minimum power ramp rate is 50 μs. --- Quote End --- You particularly need to look for overshoot on any of these rails. These devices are not very tolerant, for very long, of much overshoot on certain rails. 'Monotonic rise' is also important. If something else on the board suddenly loads one of the FPGA rails part way through power up it'll affect the monotonicity of the rail's rise. I'd argue such a fault is a design issue so look to your design engineers if you find anything you don't like. Cheers, Alex
