Interfacing FPGA with real hardware

IIRC the megafunction ROM has a rden (read enable) input.

Then, you must provide simple glue logic to interface /OE /CE signals coming from external processor.

A single AND with negated inputs (namely active high OE, CE) could be enough:

rden = OE AND CE

You also need to tristate the FPGA-ROM data output when /OE il high, to avoid bus contention.

The megafunction ROM also requires a clock. Use any clock available in fpga. Take care it has a period shorted than the processor read cycle; if you can't accomplish this, your processor should add wait states for ROM reads.

Oh no :(

rden is only available with Cyclone III

It's OK, you just need to add some logic yourself to achieve the desired behavior.

Are you using HDL or schematic entry?

Do not worry about the "rden" port. What it does is disable the ROM read logic to save a bit of power. It does not put the ROM's outputs in high impedance, as you need.

In fact, FPGAs only truly support high impedance in the pins' output buffers, so no internal logic blocks actually use tri-state.

So, what you need to do is to add a ROM block, then connect the ROM blocks to tri-state output buffers (alt_outbuf_tri?) and those to the pin.

Add a bit of logic to tri-state the buffers when /OE or /CE is "1".

And you're done.

Thanks for your help

I've done this :

https://www.alteraforum.com/forum/attachment.php?attachmentid=7035

I have a 275023 error :width mismatch in D7[7..0]

I can't change node to bus in the alt_outbuf_tri.

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I have a 275023 error :width mismatch in D7[7..0]

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The only problem I see is that the bus has the same name at both sides of the buffer which can't work.

Can't help there, I'm clueless about Quartus schematic entry.

I strongly recommend you learn to use an HDL for your designs.

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I can't change node to bus in the alt_outbuf_tri.

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Double click the bus conduit on the left of alt_outbuf and modify the name.