Interfacing FPGA with real hardware

IIRC the megafunction ROM has a rden (read enable) input.

Then, you must provide simple glue logic to interface /OE /CE signals coming from external processor.

A single AND with negated inputs (namely active high OE, CE) could be enough:

rden = OE AND CE

You also need to tristate the FPGA-ROM data output when /OE il high, to avoid bus contention.

The megafunction ROM also requires a clock. Use any clock available in fpga. Take care it has a period shorted than the processor read cycle; if you can't accomplish this, your processor should add wait states for ROM reads.