Hi There! Bit of a dumb question but can I directly interface a 10k10 to a 5v CMOS device or do I need to use pull-ups? From what I can tell it outputs *just* above 3.5v (on a 5v core/IO voltage) so it should be okay, right? Thanks! -Mux

--- Quote Start --- Bit of a dumb question but can I directly interface a 10k10 to a 5v CMOS device or do I need to use pull-ups? From what I can tell it outputs *just* above 3.5v (on a 5v core/IO voltage) so it should be okay, right? --- Quote End --- Direct interfacing should be fine. Check the data sheet of the device the FPGA interfaces to and see what its input high minimum is. If its less than 3.5V, then you don't need to worry. If it is higher than 3.5V, then you might need to do a little more testing. For example, actually drive the device with an FPGA output and measure the voltage. Worst-case if the device does not recognize 3.5V as a logic high, you would then need to add a pull-up, but you would also have to change your FPGA logic to drive-high and then tri-state (you want to drive high first so that the output gets to 3.5V fast). Cheers, Dave

--- Quote Start --- Direct interfacing should be fine. Check the data sheet of the device the FPGA interfaces to and see what its input high minimum is. If its less than 3.5V, then you don't need to worry. If it is higher than 3.5V, then you might need to do a little more testing. For example, actually drive the device with an FPGA output and measure the voltage. Worst-case if the device does not recognize 3.5V as a logic high, you would then need to add a pull-up, but you would also have to change your FPGA logic to drive-high and then tri-state (you want to drive high first so that the output gets to 3.5V fast). Cheers, Dave --- Quote End --- Yeah, that's what I figured. VIH is listed as 2.2v min which should give it plenty of margin. Thanks for the quick reply Dave! -Mux

--- Quote Start --- Bit of a dumb question but can I directly interface a 10k10 to a 5v CMOS device or do I need to use pull-ups? From what I can tell it outputs *just* above 3.5v (on a 5v core/IO voltage) so it should be okay, right? --- Quote End --- Did you read the datasheet throughly? Flex10k outputs driving CMOS (effectively zero Ioh) have full CMOS swing (Voh > 4.0V).

Must've missed that. Got a page number? I measured ~3.5v, hence my question... Either way, the device I'm interfacing accepts anything > 2.2v, so I'm good :-) -Mux

--- Quote Start --- Must've missed that. Got a page number? I measured ~3.5v, hence my question... Either way, the device I'm interfacing accepts anything > 2.2v, so I'm good :-) --- Quote End --- Here's a copy of the FLEX10K data sheet, I couldn't find a link on Altera's site. The information you want is in Table 19 on p44, and in Figure 20 on p46. The output high voltage depends on how much current your external device is drawing. If you really were driving a high-impedance input and were drawing no current, then Figure 20 indicate you should get a high voltage of 4V. Since you are getting 3.5V, either your VCCIO voltage is low, or your external device is drawing a few milliamps. As you comment, your interface logic levels are compatible, so you're fine. Cheers, Dave

interfacing Flex10k10 to CMOS | Altera Community

13 Replies

Altera_Forum
Honored Contributor
13 years ago
--- Quote Start ---
If its an all 5V system, then why would you suggest you are using VCCIO = 3.3V? :)
--- Quote End ---

I wasn't :-) That's why it probably came across as confusing...

--- Quote Start ---
I'm not sure that anything really changes in the I/O cells based on these selections. I recall that selecting between standards gives you more current drive options in some of the newer devices, but I don't recall the FLEX10Ks as having a lot of flexibility. It may be that these settings are more "you telling the tool about the PCB" rather than the tool using those settings to set a bit in the configuration bit stream.

Either way, the I/Os are 5V tolerant, so you can try both. Generate a toggling signal and look at it with a scope for each setting.

Cheers,
Dave
--- Quote End ---

Yeah, either of the settings work which is somewhat puzzling. Right now I've been wrestling with some issues on my own PCB where I'm seeing some erratic behavior. Been poking around with a logic probe but looks like I need to bring out my scope..

-Mux
Altera_Forum
Honored Contributor
13 years ago
--- Quote Start ---

looks like I need to bring out my scope...
--- Quote End ---

Yep :)

Good luck!

Cheers,
Dave
Altera_Forum
Honored Contributor
13 years ago
No matter how crappy a logic analyzer you have (USBEE-SX in my case), a picture is worth a thousand words.

On the Z80, the \RD line goes about the same time as \MREQ goes low, so I gated my CS based on that since it's actually ram I didn't want to scribble over. In my all-mighty wisdom I figured that decoding ram should therefore be (\RDd&\WR) which nicely gated / killed my address setup time to coincide with the write-pulse, resulting in err, junk..

Since signal-tap isn't supported on 10K10 devices, I'm considering upgrading to a LogicPort analyzer. Anyone have good / bad things to say about that one (or perhaps willing to sell me theirs? )

-Mux

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interfacing Flex10k10 to CMOS

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