Honored Contributor
Honored ContributorNo matter how crappy a logic analyzer you have (USBEE-SX in my case), a picture is worth a thousand words.
On the Z80, the \RD line goes about the same time as \MREQ goes low, so I gated my CS based on that since it's actually ram I didn't want to scribble over. In my all-mighty wisdom I figured that decoding ram should therefore be (\RDd&\WR) which nicely gated / killed my address setup time to coincide with the write-pulse, resulting in err, junk.. Since signal-tap isn't supported on 10K10 devices, I'm considering upgrading to a LogicPort analyzer. Anyone have good / bad things to say about that one (or perhaps willing to sell me theirs? ) -Mux
