Hello friends, I have 2 circuits viz cir1 and cir 3. Now i want to link these 2 circuits via an independent entity say-cir2. In other words cir2 will act as a bridge between cir1 and cir3. i have independent vhdl files for both cir1 and cir3 i.e cir1.vhd and cir3.vhd. How do i write the code for cir2? How can i call the 2 circuits i.e cir1 and cir3 via the cir2 code? Pls assist me. Thanks, Vinod.

cir 2 is actually a wrapper around cir1 and cir3 here is an example (Im assuming cir1/2/3 are all separate files): entity cir1 is port ( input : in std_logic; output : out std_logic; ); end entity cir1; entity cir3 is port ( input : in std_logic; output : out std_logic; ); end entity cir1; --To connect them: entity cir2 port ( --add ports if you need them ); end entity cir2; architecture struct of cir2 is signal cir1_to_cir3 : std_logic; signal cir3_to_cir1 : std_logic; begin cir1_inst : entity work.cir1 port map ( input => cir3_to_cir1, output => cir1_to_cir3 ); cir3_inst : entity work.cir3 port map ( input => cir1_to_cir3, output => cir3_to_cir1 ); end architecture struct;

Hello Sir, Thanks for the reply. u r right they are all in different files viz cir1.vhd,cir2.vhd and cir3.vhd. Now u mentioned the entities at the top of the code for both cir1 and cir2.will i need to just declare the entities there or also the architecture as well? So basically i shall write a new code for cir3 viz- cir3.vhd and follow the steps stated by you. also, as to "entity work.cir1" - this means that we need all the 3 vhdl files in the same work directory,right sir? Thanks, Vinod.

--- Quote Start --- Hello Sir, Thanks for the reply. u r right they are all in different files viz cir1.vhd,cir2.vhd and cir3.vhd. Now u mentioned the entities at the top of the code for both cir1 and cir2.will i need to just declare the entities there or also the architecture as well? --- Quote End --- no, you dont need the entites at the top of cir2.vhd. They were just there to illustrate the port maps. --- Quote Start --- So basically i shall write a new code for cir3 viz- cir3.vhd and follow the steps stated by you. also, as to "entity work.cir1" - this means that we need all the 3 vhdl files in the same work directory,right sir? Thanks, Vinod. --- Quote End --- they dont need to be the same working directory, just compiled into the same library. In VHDL the default local library is called "work".

Hi Sir, Thanks again. what i did was design cir1 and cir3 in seperate vhdl files. then i designed another vhdl file named cir2.vhd. in this i did a port map. In cir1 we have 3 inputs and 3 outputs. while in cir3 we have 3 i/ps and 4 o/ps. which implies cir2 shall have 3 i/ps and 3 o/ps. But when i do a port map i only need to map o/ps of cir1 to i/ps of cir2 and o/p of cir2 to i/p of cir3. This basically means that i/p to cir1 and o/p to cir3 will be left floating and i am unable to use the portmap statement. Any suggestions sir?

Why have you got inputs floating? Usually, floating inputs will mean things wont work properly.

interface code | Altera Community

15 Replies

Altera_Forum
Honored Contributor
15 years ago
architecture struct of cir2 is
signal a,b,c : std_lgoic;
begin
cir1_inst : entity work.cir1
port map (x1,y1,z1, a,b,c); --- sir pls note this step. Where can i map a,b and c ?

cir3_inst : entity work.cir3
port map (a,b,c, x2,y2,z2);
Altera_Forum
Honored Contributor
15 years ago
Dear Sir,

Thanks again. i shall show the code that i used. There are no errors on comilation. but on simulating no waves are generated

cir1.vhd

library ieee;
use ieee.std_logic_1164.all;
entity cir1 is
port(a,b,c:in std_logic;
x,y,z:out std_logic);
end cir1;

architecture behavioural of cir1 is
begin
x <= (not a and not b) or (not b and not c) or (a and not c);
y <= (not a and not b) or (not a and not c);
z <= (not a and not b) or (a and b);
end behavioural;

cir3.vhd
library ieee;
use ieee.std_logic_1164.all;
entity cir3 is
port(x,y,z:in std_logic;
p,q,r,s:out std_logic);
end cir3;

architecture behavioural of cir3 is
begin
p <= (not z ) or (not x and not y and z);
q <= (not x and not y and z) or (x and y and z);
r <= (not x and y) or (x and not y and not z);
s <= not x;
end behavioural;

cir2.vhd
library ieee;
use ieee.std_logic_1164.all;
entity cir2 is
port(x1,y1,z1:in std_logic;
x2,y2,z2:out std_logic);
end cir2;

architecture struct of cir2 is
signal a,b,c,p,q,r,s:std_logic;
begin
cir1_inst : entity work.cir1
port map (x1,y1,z1,a,b,c);
cir2_inst : entity work.cir2
port map (a,b,c,x2,y2,z2);
end struct;

my cir2.do file is also pasted

quit -sim
vsim cir3
view wave
add wave a
add wave b
add wave c
add wave p
add wave q
add wave r
add wave s
force a 0 50,0 100,0 150,0 200,1 250,1 300,1 350,1 400 -repeat 400
force b 0 50,0 100,1 150,1 200,0 250,0 300,1 350,1 400 -repeat 400
force c 0 50,1 100,0 150,1 200,0 250,1 300,0 350,1 400 -repeat 400
run 800ns

.I don't get any o/ps.

Again , thanks for ur time. I really appreciate it sir.

Regards,
Vinod Karuvat.
Altera_Forum
Honored Contributor
15 years ago
you need to force x1,y1,z1 as these are the top level inputs. Not a/b/c. a,b,c are just interconnect wires between two entities. You are not seeing any waves because x2,y2 and z2 are the outputs. p,q,r,s do not exist in cir2, they only exist in cir3
Altera_Forum
Honored Contributor
15 years ago
Wow. i did not even think about that sir. but is there any way i can test this whole circuit. in other words , i just provide the i/ps a,b and c and i get the o/p p,q,r and s?

Regards,
Vinod.
Altera_Forum
Honored Contributor
15 years ago
you would be doing that by forcing x1,y1,z1. I think you are confusing yourself by calling the inputs to cir2 x1,y1,z1 when the inputs to cir1 are a,b,c. Maybe change the names of the top level inputs to a,b,c and the internal signals to x,y,z

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