interface code

Dear Sir,

Thanks again. i shall show the code that i used. There are no errors on comilation. but on simulating no waves are generated

cir1.vhd

library ieee;

use ieee.std_logic_1164.all;

entity cir1 is

port(a,b,c:in std_logic;

x,y,z:out std_logic);

end cir1;

architecture behavioural of cir1 is

begin

x <= (not a and not b) or (not b and not c) or (a and not c);

y <= (not a and not b) or (not a and not c);

z <= (not a and not b) or (a and b);

end behavioural;

cir3.vhd

library ieee;

use ieee.std_logic_1164.all;

entity cir3 is

port(x,y,z:in std_logic;

p,q,r,s:out std_logic);

end cir3;

architecture behavioural of cir3 is

begin

p <= (not z ) or (not x and not y and z);

q <= (not x and not y and z) or (x and y and z);

r <= (not x and y) or (x and not y and not z);

s <= not x;

end behavioural;

cir2.vhd

library ieee;

use ieee.std_logic_1164.all;

entity cir2 is

port(x1,y1,z1:in std_logic;

x2,y2,z2:out std_logic);

end cir2;

architecture struct of cir2 is

signal a,b,c,p,q,r,s:std_logic;

begin

cir1_inst : entity work.cir1

port map (x1,y1,z1,a,b,c);

cir2_inst : entity work.cir2

port map (a,b,c,x2,y2,z2);

end struct;

my cir2.do file is also pasted

quit -sim

vsim cir3

view wave

add wave a

add wave b

add wave c

add wave p

add wave q

add wave r

add wave s

force a 0 50,0 100,0 150,0 200,1 250,1 300,1 350,1 400 -repeat 400

force b 0 50,0 100,1 150,1 200,0 250,0 300,1 350,1 400 -repeat 400

force c 0 50,1 100,0 150,1 200,0 250,1 300,0 350,1 400 -repeat 400

run 800ns

.I don't get any o/ps.

Again , thanks for ur time. I really appreciate it sir.

Regards,

Vinod Karuvat.