Honored ContributorHello friends,
I have 2 circuits viz cir1 and cir 3. Now i want to link these 2 circuits via an independent entity say-cir2. In other words cir2 will act as a bridge between cir1 and cir3. i have independent vhdl files for both cir1 and cir3 i.e cir1.vhd and cir3.vhd. How do i write the code for cir2? How can i call the 2 circuits i.e cir1 and cir3 via the cir2 code? Pls assist me. Thanks, Vinod.
Honored Contributorcir 2 is actually a wrapper around cir1 and cir3
here is an example (Im assuming cir1/2/3 are all separate files):
entity cir1 is
port (
input : in std_logic;
output : out std_logic;
);
end entity cir1;
entity cir3 is
port (
input : in std_logic;
output : out std_logic;
);
end entity cir1;
--To connect them:
entity cir2
port (
--add ports if you need them
);
end entity cir2;
architecture struct of cir2 is
signal cir1_to_cir3 : std_logic;
signal cir3_to_cir1 : std_logic;
begin
cir1_inst : entity work.cir1
port map (
input => cir3_to_cir1,
output => cir1_to_cir3
);
cir3_inst : entity work.cir3
port map (
input => cir1_to_cir3,
output => cir3_to_cir1
);
end architecture struct;
Hello Sir,
Thanks for the reply. u r right they are all in different files viz cir1.vhd,cir2.vhd and cir3.vhd. Now u mentioned the entities at the top of the code for both cir1 and cir2.will i need to just declare the entities there or also the architecture as well? So basically i shall write a new code for cir3 viz- cir3.vhd and follow the steps stated by you. also, as to "entity work.cir1" - this means that we need all the 3 vhdl files in the same work directory,right sir? Thanks, Vinod.Honored ContributorHonored ContributorHi Sir,
Thanks again. what i did was design cir1 and cir3 in seperate vhdl files. then i designed another vhdl file named cir2.vhd. in this i did a port map. In cir1 we have 3 inputs and 3 outputs. while in cir3 we have 3 i/ps and 4 o/ps. which implies cir2 shall have 3 i/ps and 3 o/ps. But when i do a port map i only need to map o/ps of cir1 to i/ps of cir2 and o/p of cir2 to i/p of cir3. This basically means that i/p to cir1 and o/p to cir3 will be left floating and i am unable to use the portmap statement. Any suggestions sir?Honored ContributorWhy have you got inputs floating?
Usually, floating inputs will mean things wont work properly.Honored ContributorHello Sir,
Thanks again. I shall attach an image 2 show u my circuit. Pls check out the i/p for cir1 and o/ps for cir3. My aim is to design cir2 ina different vhdl file. Regards, VinodHonored Contributorthere are no floting inputs or outputs in that diagram.
Honored ContributorHello Sir,
a,b,c ,p,q,r, and s are floating. the code i wrote was - library ieee; use ieee.std_logic_1164.all; entity cir2 is port(x1,y1,z1:in std_logic; x2,y2,z2:out std_logic); end cir2; architecture struct of cir2 is begin cir1_inst : entity work.cir1 port map (x1,y1,z1); --- sir pls note this step. Where can i map a,b and c ? cir3_inst : entity work.cir3 port map (x2,y2,z2); -- Likewise here where can I map x1,y1 and z1? Sorry to trouble u sir. Regards, Vinod.Honored Contributorthe code you have posted does not match the diagram you posted.
this diagram represents your code.Honored ContributorYes sir.u r right. so how do I go about with this port map pls? cld u kindly give me a sample code for this pls?
Regards, Vinod.
