Hi David,
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I would like to interface a TI ADC08D1520 to a Cyclone III.
It has dual data rate, diff pair outputs, that are electrically compatible with LVDS.
At max speed, the data clock (also an LVDS compatible diff pair) runs at 375MHz, and is supposed to clock the data on both edges. Ie the data rate is 750MHz.
Does anyone have direct experience with trying to get a Cyclone III to run this fast?
Will I need a Stratix series part instead?
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I looked at 1GHz clock-rate National Semiconductor ADCs when I was designing this board:
http://www.ovro.caltech.edu/~dwh/carma_board/ (
http://www.ovro.caltech.edu/%7edwh/carma_board/)
I ended up using the dual-channel 1GHz e2v ADC, since it had independent clocks. I needed the logic density of the Stratix II devices. Look at the documents on that page, eg.,
http://www.ovro.caltech.edu/~dwh/carma_board/digitizer_tests.pdf (
http://www.ovro.caltech.edu/%7edwh/carma_board/digitizer_tests.pdf)
As it has a lot of info on the LVDS interfacing.
I believe you could interface to the Cyclone parts at the data rate you desire. However, you might want to check your signal processing logic requirements before you commit to the final design.
The schematics and PCB layout are there on that page too. Feel free to use any parts of the design, eg., the 1GHz clock generator logic (changed to your application frequency of course).
The Berkeley CASPER group has a number of boards with National ADCs on them too:
https://casper.berkeley.edu/wiki/hardware Cheers,
Dave
Honored Contributor
