interface ADC0804 with CPLD

That... will not work.

What you have can be summarized as (in a cleaner way)

clk_out <= not clk_in;
process(clk_out)
begin
if(clk_out'event and clk_out='1') then
    count <=count+1;
    if(count = 5) then
        clk <= not clk;
        count <= 1;
--        cs <= '0'; -- overriden
--        wr<='0';  -- overriden
        wr<='0';
        cs<='1';
        if(intr = '0') then
            flag <= '1';
        end if;
    end if;
end if;
end process;

Don't abuse "buffer". Use "in", "out" and "inout" as needed.

You mention that you want 1 MHz for the ADC and 500 kHz for the CPLD, but in your code, logic is running in the (negated) input clock, not in the divided by 2 "clk".