library ieee;
use ieee.std_logic_1164.all;
entity adc is
port 
(
cs : buffer std_logic;
rd : buffer std_logic;
wr : buffer std_logic;
intr :buffer std_logic;
clk_in: in std_logic;
flag: buffer std_logic;
clk_out: buffer std_logic;
clk: buffer std_logic
);
end adc;
architecture behave of adc is
signal count: integer range 5 downto 0;
begin
process(all)
begin


clk_out <= not clk_in;
if(clk_out'event and clk_out='1') then
count <=count+1;
if(count = 5) then
clk <= not clk;
count <= 1;
cs <= '0';
if(count = 5) then
clk <= not clk;
count <= 1;
wr<='0';
if(count = 5) then
clk <= not clk;
count <= 1;
wr<='1';
if(count = 5) then
clk <= not clk;
count <= 1;
cs<='1';
if(count = 5) then
clk <= not clk;
count <= 1;
if(intr = '0') then
flag <='1';
end if;
end if;
end if;
end if;
end if;
end if;
end if;
end process;
end behave;